SN74V273PZAEP Купить - TI FIFO

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SN74V273PZAEP

FIFO Mem Sync Dual Depth/Width Uni-Dir 16K x 18/32K x 9 80Pin LQFP

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ЧипСити Номер продукта:

CC61257503

Категория продукта:

FIFO

Дата доставки: 7 дней

3D модель

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Обновлено 24.04.2026, 07:48:07(GMT+3)

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SN74V273PZAEP характеристики

Атрибут	Значение атрибута
Номенклатура	SN74V273PZAEP
Производитель	TI
ЧипСити Номер продукта	CC61257503
Жизненный Цикл Продукта	Active
Категория продукта	FIFO
Даташит
3D модель	3D модель
Стиль Монтажа	Surface Mount
Количество Выводов	80 Pin
Корпус/Пакет	LQFP-80
Частота	133 MHz
Напряжение Питания (DC)	3.15V ~ 3.45V
Количество Цепей	2 Circuit
Узлы Напряжения	3.30 V
Время Доступа	5 ns
Привод Выходного Тока	-250 µA
Время доступа (Макс)	5 ns
Рабочая температура (Макс)	125 ℃
Рабочая температура (мин)	-55 ℃
Напряжение питания	3.15V ~ 3.45V
Ширина	14 mm
Высота	1.4 mm
Рабочая Температура	-55℃ ~ 125℃
Упаковка	Tray
RoHS Комплаенс	RoHS Compliant
Бессвинцовая Статус	Lead Free
ECCN кодекс	3A991.b.2.b
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SN74V273PZAEP описание продукта

The SN74V263, SN74V273, SN74V283, and SN74V293 are exceptionally deep, high-speed, CMOS first-in first-out (FIFO) memories with clocked read and write controls and a flexible bus-matching ×9/×18 data flow.
There is flexible ×9/×18 bus matching on both read and write ports.
The period required by the retransmit operation is fixed and short.
The first-word data-latency period, from the time the first word is written to an empty FIFO to the time it can be read, is fixed and short.
These FIFOs are particularly appropriate for network, video, telecommunications, data communications, and other applications that need to buffer large amounts of data and match buses of unequal sizes.
Each FIFO has a data input port (Dn) and a data output port (Qn), both of which can assume either an 18-bit or 9-bit width, as determined by the state of external control pins input width (IW) and output width (OW) during the master-reset cycle.
The input port is controlled by write-clock (WCLK) and write-enable (WEN)\ inputs. Data is written into the FIFO on every rising edge of WCLK when WEN\ is asserted. The output port is controlled by read-clock (RCLK) and read-enable (REN\\\\) inputs. Data is read from the FIFO on every rising edge of RCLK when REN\ is asserted. An output-enable (OE\\\\) input is provided for 3-state control of the outputs.
The frequencies of both the RCLK and the WCLK signals can vary from 0 to fMAX, with complete independence. There are no restrictions on the frequency of one clock input with respect to the other.
There are two possible timing modes of operation with these devices: first-word fall-through (FWFT) mode and standard mode.
In FWFT mode, the first word written to an empty FIFO is clocked directly to the data output lines after three transitions of the RCLK signal. REN\ need not be asserted for accessing the first word. However, subsequent words written to the FIFO do require a low on REN\ for access. The state of the FWFT/SI input during master reset determines the timing mode in use.
In standard mode, the first word written to an empty FIFO does not appear on the data output lines unless a specific read operation is performed. A read operation, which consists of activating REN\ and enabling a rising RCLK edge, shifts the word from internal memory to the data output lines.
For applications requiring more data-storage capacity than a single FIFO can provide, the FWFT timing mode permits depth expansion by chaining FIFOs in series (i.e., the data outputs of one FIFO are connected to the corresponding data inputs of the next). No external logic is required.
These FIFOs have five flag pins: empty flag or output ready (EF\/OR\\\\), full flag or input ready (FF\/IR\\\\), half-full flag (HF)\, programmable almost-empty flag (PAE)\, and programmable almost-full flag (PAF)\\\\. The IR\ and OR\ functions are selected in FWFT mode. The EF\ and FF\ functions are selected in standard mode. HF\, PAE\, and PAF\ always are available for use, regardless of timing mode.
PAE\ and PAF\ can be programmed independently to switch at any point in memory. Programmable offsets determine the flag-switching threshold and can be loaded by parallel or serial methods. Eight default offset settings also are provided, so that PAE\ can be set to switch at a predefined number of locations from the empty boundary. The PAF\ threshold also can be set at similar predefined values from the full boundary. The default offset values are set during master reset by the state of FSEL0, FSEL1, and LD\\\\.
For serial programming, SEN\, together with LD\, loads the offset registers via the serial input (SI) on each rising edge of WCLK. For parallel programming, WEN\, together with LD\, loads the offset registers via Dn on each rising edge of WCLK. REN\, together with LD\, can read the offsets in parallel from Qn on each rising edge of RCLK, regardless of whether serial or parallel offset loading has been selected.
Also, the timing modes of PAE\ and PAF\ outputs can be selected. Timing modes can be set to be either asynchronous or synchronous for PAE\ and PAF\\\\.
If the asynchronous PAE\/PAF\ configuration is selected, PAE\ is asserted low on the low-to-high transition of RCLK. PAE\ is reset to high on the low-to-high transition of WCLK. Similarly, PAF\ is asserted low on the low-to-high transition of WCLK, and PAF\ is reset to high on the low-to-high transition of RCLK.
If the synchronous PAE\/PAF\ configuration is selected , PAE\ is asserted and updated on the rising edge of RCLK only and not WCLK. Similarly, PAF\ is asserted and updated on the rising edge of WCLK only and not RCLK. The desired mode is configured during master reset by the state of the programmable-flag mode (PFM) pin.
The retransmit function allows data to be reread from the FIFO more than once. A low on the RT\ input during a rising RCLK edge initiates a retransmit operation by setting the read pointer to the first location of the memory array. Zero-latency retransmit timing mode can be selected using the retransmit timing mode (RM). During master reset, a low on RM selects zero-latency retransmit. A high on RM during master reset selects normal latency.
If zero-latency retransmit operation is selected, the first data word to be retransmitted is placed on the output register with respect to the same RCLK edge that initiated the retransmit, if RT\ is low.
During master reset (MRS)\, the functions for all the operating modes are programmed. These include FWFT or standard timing, input bus width, output bus width, big endian or little endian, retransmit mode, programmable-flag operating and programming method, programmable-flag default offsets, and interspersed parity select. The read and write pointers are set to the first location of the FIFO. Then, based on the selected timing mode, EF\ is set low or OR\ is set high and FF\ is set high or IR\ is set low. Also, PAE\ is set low, PAF\ is set high, and HF\ is set high. The Q outputs are set low.
Partial reset (PRS\\\\) also sets the read and write pointers to the first location of the memory. However, the timing mode, programmable-flag programming method, default or programmed offset settings, input and output bus widths, big endian/little endian, interspersed parity select, and retransmit mode (existing before partial reset is asserted) remain unchanged. The flags are updated according to the timing mode and offsets in effect. PRS\ is useful for resetting a device in mid-operation when reprogramming programmable flags and other functions would be undesirable.
A big-endian/little-endian data word format is provided. This function is useful when data is written into the FIFO in long-word (×18) format and read out of the FIFO in small-word (×9) format. If big-endian mode is selected, the most significant byte (MSB) (word) of the long word written into the FIFO is read out of the FIFO first, followed by the least-significant byte (LSB). If little-endian format is selected, the LSB of the long word written into the FIFO is read out first, followed by the MSB. The mode desired is configured during master reset by the state of the big-endian/little-endian (BE)\ pin.
The interspersed/noninterspersed parity (IP) bit function allows the user to select the parity bit in the word loaded into the parallel port (D0Dn) when programming the flag offsets. If interspersed-parity mode is selected, the FIFO assumes that the parity bit is located in bit position D8 during the parallel programming of the flag offsets. If noninterspersed-parity mode is selected, D8 is assumed to be a valid bit and D16 and D17 are ignored. IP mode is selected during master reset by the state of the IP input pin. This mode is relevant only when the input width is set to ×18 mode.
The SN74V263, SN74V273, SN74V283, and SN74V293 are fabricated using TIs high-speed submicron CMOS technology.
For more information on this device family, see the following application reports:

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