PN5120A0HN/C1,551 Купить - NXP Активная деталь

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PN5120A0HN/C1,551

NXP

RFID Reader/Transponder IC 13.56MHz FeliCa, ISO 14443, MIFARE, NFC I2C, SPI, UART 2.5V ~ 3.6V 40-VFQFN Exposed Pad

Наличие: 290 шт. Гарантия оригинала

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Цена: ₽ 358.99

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Производитель:

NXP

ЧипСити Номер продукта:

CC77781419

Категория продукта:

Активная деталь

Дата доставки: 7 дней

3D модель

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PN5120A0HN/C1,551 характеристики

Атрибут	Значение атрибута
Номенклатура	PN5120A0HN/C1,551
Производитель	NXP
ЧипСити Номер продукта	CC77781419
Жизненный Цикл Продукта	Active
Категория продукта	Активная деталь
Даташит
3D модель	3D модель
Стиль Монтажа	Surface Mount
Количество Выводов	40 Pin
Корпус/Пакет	VFQFN-40
Частота	13.56 MHz
Напряжение Питания (DC)	2.50V (min)
Количество Стежков	40 Position
Рабочая температура (Макс)	85 ℃
Рабочая температура (мин)	-30 ℃
Напряжение питания	2.5V ~ 3.6V
Напряжение питания (Макс)	3.6 V
Напряжение питания (мин)	2.5 V
Вес	89.8 mg
Рабочая Температура	-40℃ ~ 90℃
Упаковка	Cut Tape (CT)
RoHS Комплаенс	RoHS Compliant
Бессвинцовая Статус	Lead Free
REACH SVHC Комплаенс	No SVHC
REACH SVHC Compliance Edition	2015/12/17
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PN5120A0HN/C1,551 описание продукта

Overview
PN512 is the most broadly adopted NFC frontend - powering more than 10 billion NFC transactions per year.
It is a highly integrated NFC frontend for contactless communication at 13.56 MHz. This NFC frontend utilizes an outstanding modulation and demodulation concept completely integrated for different kinds of contactless communication methods and protocols at 13.56 MHz.
The PN512 NFC frontend supports 4 different operating modes:
* Reader/Writer mode supporting ISO/IEC 14443A/MIFARE and FeliCa scheme
* Reader/Writer mode supporting ISO/IEC 14443B
* Card Operation mode supporting ISO/IEC 14443A/MIFARE and FeliCa scheme
* NFCIP-1 mode
Enabled in Reader/Writer mode for ISO/IEC 14443A/MIFARE, the PN512’s internal transmitter part is able to drive a reader/writer antenna designed to communicate with ISO/IEC 14443A/ MIFARE cards and transponders without additional active circuitry. The receiver part provides a robust and efficient implementation of a demodulation and decoding circuitry for signals from ISO/IEC 14443A/MIFARE compatible cards and transponders. The digital part handles the complete ISO/IEC 14443A framing and error detection (Parity and CRC).
Enabled in Reader/Writer mode for FeliCa, the PN512 NFC frontend supports the FeliCa communication scheme. The receiver part provides a robust and efficient implementation of the demodulation and decoding circuitry for FeliCa coded signals. The digital part handles the FeliCa framing and error detection like CRC. The PN512 supports contactless communication using FeliCa Higher transfer speeds up to 424 kbit/s in both directions.
The PN512 supports all layers of the ISO/IEC 14443B reader/writer communication scheme, given correct implementation of additional components, like oscillator, power supply, coil etc. and provided that standardized protocols, e.g. like ISO/IEC 14443-4 and/or ISO/IEC 14443B anticollision are correctly implemented.
In Card Operation mode, the PN512 NFC frontend is able to answer to a reader/writer command either according to the FeliCa or ISO/IEC 14443A/MIFARE card interface scheme. The PN512 generates the digital load modulated signals and in addition with an external circuit the answer can be sent back to the reader/writer. A complete card functionality is only possible in combination with a secure IC using the S²C interface.
Additionally, the PN512 NFC frontend offers the possibility to communicate directly to an NFCIP-1 device in the NFCIP-1 mode. The NFCIP-1 mode offers different communication mode and transfer speeds up to 424 kbit/s according to the Ecma 340 and ISO/IEC 18092 NFCIP-1 Standard. The digital part handles the complete NFCIP-1 framing and error detection.
Various host controller interfaces are implemented:
* 8-bit parallel interface
* SPI interface
* serial UART (similar to RS232 with voltage levels according pad voltage supply)
* I²C interface
### Different available versions
The PN512 is available in three versions:
* PN5120A0HN1/C2 (HVQFN32), PN5120A0HN/C2 (HVQFN40) and PN5120A0ET/C2 (TFBGA64), hereafter named as version 2.0
* PN512AA0HN1/C2 (HVQFN32) and PN512AA0HN1/C2BI (HVQFN32 with Burn In), hereafter named as industrial version, fulfilling the automotive qualification stated in AEC-Q100 grade 3 from the Automotive Electronics Council, defining the critical stress test qualification for automotive integrated circuits (ICs).
* PN5120A0HN1/C1(HVQFN32) and PN5120A0HN/C1 (HVQFN40), hereafter named as version 1.0
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## Features
* Includes NXP’s intellectual property licensing rights (required for ISO/IEC 14443A implementation)
* Fast and cost-efficient NFC design startup
* Highly integrated analog circuitry to demodulate and decode responses
* Buffered output drivers for connecting an antenna with the minimum number of external components
* Integrated RF Level detector
* Integrated data mode detector
* Supports ISO/IEC 14443 A/MIFARE
* Supports ISO/IEC 14443 B Read/Write modes
* Typical operating distance in Read/Write mode up to 50 mm depending on the antenna size and tuning
* Typical operating distance in NFCIP-1 mode up to 50 mm depending on the antenna size and tuning and power supply
* Typical operating distance in ISO/IEC 14443A/MIFARE card or FeliCa Card Operation mode of about 100 mm depending on the antenna size and tuning and the external field strength
* Supports MIFARE Classic encryption in Reader/Writer mode
* ISO/IEC 14443A higher transfer speed communication at 212 kbit/s and 424 kbit/s
* Contactless communication according to the FeliCa scheme at 212 kbit/s and 424 kbit/s
* Integrated RF interface for NFCIP-1 up to 424 kbit/s
* S²C interface
* Additional power supply to directly supply the smart card IC connected via S²C
* Supported host interfaces:
* SPI up to 10 Mbit/s
* I²C-bus interface up to 400 kBd in Fast mode, up to 3400 kBd in High-speed mode
* RS232 Serial UART up to 1228.8 kBd, with voltage levels dependant on pin voltage supply
* 8-bit parallel interface with and without Address Latch Enable
* FIFO buffer handles 64 byte send and receive
* Flexible interrupt modes
* Hard reset with low power function
* Power-down mode per software
* Programmable timer
* Internal oscillator for connection to 27.12 MHz quartz crystal
* 2.5 V to 3.6 V power supply
* CRC coprocessor
* Programmable I/O pins
* Internal self-test
## Features

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