TMS320C6713BZDP225 Купить - TI Цифровой сигнальный процессор DSP

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TMS320C6713BZDP225

DSP Floating-Point 32Bit 225MHz 1800MIPS 272Pin BGA

Наличие: 1,102 шт. Гарантия оригинала

Адрес доставки: Москва

Цена: ₽ 3,791.09

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ЧипСити Номер продукта:

CC21027760

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Цифровой сигнальный процессор DSP

Дата доставки: 7 дней

3D модель

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TMS320C6713BZDP225 характеристики

Атрибут	Значение атрибута
Номенклатура	TMS320C6713BZDP225
Производитель	TI
ЧипСити Номер продукта	CC21027760
Жизненный Цикл Продукта	Active
Категория продукта	Цифровой сигнальный процессор DSP
Даташит
3D модель	3D модель
Стиль Монтажа	Surface Mount
Количество Выводов	272 Pin
Корпус/Пакет	BGA-272
Частота	225 MHz
Напряжение Питания (DC)	1.20 V
Количество Стежков	272 Position
Тактовая Частота	225 MHz
Количество Битов	32 Bit
Количество I/O Выводов	16 IO
Количество входов и выходов	16 Input IO
Рабочая температура (Макс)	90 ℃
Рабочая температура (мин)	0 ℃
Напряжение питания	3.3 V
Длина	27 mm
Ширина	27 mm
Высота	1.78 mm
Рабочая Температура	0℃ ~ 90℃
Упаковка	Tray
RoHS Комплаенс	RoHS Compliant
Бессвинцовая Статус	Lead Free
REACH SVHC Комплаенс	No SVHC
REACH SVHC Compliance Edition	2015/06/15
ECCN кодекс	3A991.a.2
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TMS320C6713BZDP225 описание продукта

The TMS320C67x DSPs (including the TMS320C6713B device) compose the floating-point DSP generation in the TMS320C6000 DSP platform. The C6713B device is based on the high-performance, advanced very-long-instruction-word (VLIW) architecture developed by Texas Instruments (TI), making this DSP an excellent choice for multichannel and multifunction applications.
Operating at 225 MHz, the C6713B delivers up to 1350 million floating-point operations per second (MFLOPS), 1800 million instructions per second (MIPS), and with dual fixed-/floating-point multipliers up to 450 million multiply-accumulate operations per second (MMACS).
Operating at 300 MHz, the C6713B delivers up to 1800 million floating-point operations per second (MFLOPS), 2400 million instructions per second (MIPS), and with dual fixed-/floating-point multipliers up to 600 million multiply-accumulate operations per second (MMACS).
The C6713B uses a two-level cache-based architecture and has a powerful and diverse set of peripherals. The Level 1 program cache (L1P) is a 4K-byte direct-mapped cache and the Level 1 data cache (L1D) is a 4K-byte 2-way set-associative cache. The Level 2 memory/cache (L2) consists of a 256K-byte memory space that is shared between program and data space. 64K bytes of the 256K bytes in L2 memory can be configured as mapped memory, cache, or combinations of the two. The remaining 192K bytes in L2 serves as mapped SRAM.
The C6713B has a rich peripheral set that includes two Multichannel Audio Serial Ports (McASPs), two Multichannel Buffered Serial Ports (McBSPs), two Inter-Integrated Circuit (I2C) buses, one dedicated General-Purpose Input/Output (GPIO) module, two general-purpose timers, a host-port interface (HPI), and a glueless external memory interface (EMIF) capable of interfacing to SDRAM, SBSRAM, and asynchronous peripherals.
The two McASP interface modules each support one transmit and one receive clock zone. Each of the McASP has eight serial data pins which can be individually allocated to any of the two zones. The serial port supports time-division multiplexing on each pin from 2 to 32 time slots. The C6713B has sufficient bandwidth to support all 16 serial data pins transmitting a 192 kHz stereo signal. Serial data in each zone may be transmitted and received on multiple serial data pins simultaneously and formatted in a multitude of variations on the Philips Inter-IC Sound (I2S) format.
In addition, the McASP transmitter may be programmed to output multiple S/PDIF, IEC60958, AES-3, CP-430 encoded data channels simultaneously, with a single RAM containing the full implementation of user data and channel status fields.
The McASP also provides extensive error-checking and recovery features, such as the bad clock detection circuit for each high-frequency master clock which verifies that the master clock is within a programmed frequency range.
The two I2C ports on the TMS320C6713B allow the DSP to easily control peripheral devices and communicate with a host processor. In addition, the standard multichannel buffered serial port (McBSP) may be used to communicate with serial peripheral interface (SPI) mode peripheral devices.
The TMS320C6713B device has two bootmodes: from the HPI or from external asynchronous ROM. For more detailed information, see the _bootmode_ section of this data sheet.
The TMS320C67x DSP generation is supported by the TI eXpressDSP set of industry benchmark development tools, including a highly optimizing C/C++ Compiler, the Code Composer Studio Integrated Development Environment (IDE), JTAG-based emulation and real-time debugging, and the DSP/BIOS kernel.

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10/27/2016